Modern integrated circuits have billions of discrete elements (e.g. transistors). Before the ultimate goal of an integrated circuit design is reached, i.e. a layout of the integrated circuit design is generated, the design of integrated circuit is generated at various abstraction levels. In some cases only high level synthesis (e.g. design at an electronic system level (ESL) of abstraction) is employed. Using high level synthesis requires utilization of pre-synthesized large block synthesis (LBS) blocks. The major work load in this approach is integration of the LBS blocks. When a library of synthesized LBS blocks is not available there is a need to generate an integrated circuit design a lower level of abstraction, e.g. at register transfer level (RTL) of abstraction. This method requires more resources, but it can provide for an integrated circuit design having a better performance in comparison with an integrated circuit design generated the high level synthesis.
Even when providing of the resources for low level synthesis is not an issue, another problem of the detailed specification of performance of the integrated circuit design at each of hierarchy levels may emerge. Although it might be relatively easy to specify a performance of a single logic gate in low level synthesis, a specification of the electronic circuit design at higher level (e.g. a macro cell or macro) might be problematic, because these specifications can imply unnecessary limitations for architectural solutions. For instance, a design of a microprocessor can be specified at high level, just by clock frequency, functionality of input/output ports, and a number of operations it has to perform per second. As a result thereof the choice of other parameters, e.g. data capacity and internal architecture of a first level cache and a second level cache, is free. Low level synthesis, e.g. at RTL of abstraction, requires these parameters to be known upfront. These parameters can be included in optimization procedure of the electronic level design at RTL of abstraction as variables. However, this approach might result in a very long design procedure because too many variables have to be optimized simultaneously.